Percepio Trace Recorder
v4.11.0
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trcDefines.h
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/*
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* Trace Recorder for Tracealyzer v4.11.0
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* Copyright 2025 Percepio AB
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* www.percepio.com
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Some common defines for the trace recorder.
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*/
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#ifndef TRC_DEFINES_H
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#define TRC_DEFINES_H
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#define TRC_SUCCESS ((traceResult)0)
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#define TRC_FAIL ((traceResult)1)
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#define TRC_FREE_RUNNING_32BIT_INCR 1
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#define TRC_FREE_RUNNING_32BIT_DECR 2
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#define TRC_OS_TIMER_INCR 3
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#define TRC_OS_TIMER_DECR 4
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#define TRC_CUSTOM_TIMER_INCR 5
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#define TRC_CUSTOM_TIMER_DECR 6
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#define TRC_STATE_IN_STARTUP 0
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#define TRC_STATE_IN_TASKSWITCH 1
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#define TRC_STATE_IN_APPLICATION 2
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/* Start options for vTraceEnable. */
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#define TRC_START_FROM_HOST 0UL
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#define TRC_START 1UL
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#define TRC_START_AWAIT_HOST 2UL
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#define TRC_ACKNOWLEDGED (0xABC99123)
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/* Command codes for TzCtrl task */
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#define CMD_SET_ACTIVE 1
/* Start (param1 = 1) or Stop (param1 = 0) */
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/* The final command code, used to validate commands. */
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#define CMD_LAST_COMMAND 1
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#define TRC_RECORDER_BUFFER_ALLOCATION_STATIC (0x00UL)
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#define TRC_RECORDER_BUFFER_ALLOCATION_DYNAMIC (0x01UL)
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#define TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM (0x02UL)
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#define TRC_OPTION_BIT_SHIFT_IRQ_ORDER 0
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#define TRC_OPTION_BIT_SHIFT_BASE_SIZE 8
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/******************************************************************************/
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/*** ERROR AND WARNING CODES (check using xTraceErrorGetLast) *****************/
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/******************************************************************************/
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#define TRC_ERROR_NONE 0x00UL
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#define TRC_ERROR_ASSERT 0x01UL
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#define TRC_ERROR_EVENT_CODE_TOO_LARGE 0x02UL
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#define TRC_ERROR_ISR_NESTING_OVERFLOW 0x03UL
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#define TRC_ERROR_DWT_NOT_SUPPORTED 0x04UL
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#define TRC_ERROR_DWT_CYCCNT_NOT_SUPPORTED 0x05UL
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#define TRC_ERROR_TZCTRLTASK_NOT_CREATED 0x06UL
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#define TRC_ERROR_STREAM_PORT_WRITE 0x07UL
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#define TRC_WARNING_ENTRY_TABLE_SLOTS 0x08UL
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#define TRC_WARNING_ENTRY_SYMBOL_MAX_LENGTH 0x09UL
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#define TRC_WARNING_EVENT_SIZE_TRUNCATED 0x0AUL
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#define TRC_WARNING_STREAM_PORT_READ 0x0BUL
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#define TRC_WARNING_STREAM_PORT_WRITE 0x0CUL
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#define TRC_WARNING_STREAM_PORT_INITIAL_BLOCKING 0x0DUL
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#define TRC_WARNING_STACKMON_NO_SLOTS 0x0EUL
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/* Entry Option definitions */
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#define TRC_ENTRY_OPTION_EXCLUDED 0x00000001UL
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#define TRC_ENTRY_OPTION_HEAP 0x80000000UL
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#define TRC_ENTRY_OPTION_EXTENSION 0x40000000UL
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#define TRC_ENTRY_OPTION_STATE_MACHINE 0x20000000UL
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#define TRC_ENTRY_OPTION_STATE_MACHINE_STATE 0x10000000UL
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#define TRC_ENTRY_OPTION_INTERVAL_CHANNEL 0x08000000UL
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#define TRC_ENTRY_OPTION_COUNTER 0x04000000UL
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#define TRC_ENTRY_OPTION_INTERVAL_CHANNEL_SET 0x02000000UL
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#define TRC_ENTRY_OPTION_IDLE_NAME 0x01000000UL
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#define TRC_ENTRY_OPTION_RUNNABLE 0x00800000UL
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#define TRC_ENTRY_OPTION_DEPENDENCY 0x00400000UL
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#define TRC_DEPENDENCY_TYPE_ELF 0x00000001UL
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#define TRC_RECORDER_COMPONENT_CORE 0x00000001UL
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#define TRC_RECORDER_COMPONENT_ASSERT 0x00000002UL
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#define TRC_RECORDER_COMPONENT_BLOB 0x00000004UL
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#define TRC_RECORDER_COMPONENT_DIAGNOSTICS 0x00000008UL
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#define TRC_RECORDER_COMPONENT_ENTRY 0x00000010UL
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#define TRC_RECORDER_COMPONENT_ERROR 0x00000020UL
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#define TRC_RECORDER_COMPONENT_EVENT 0x00000040UL
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#define TRC_RECORDER_COMPONENT_EVENT_BUFFER 0x00000080UL
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#define TRC_RECORDER_COMPONENT_EXTENSION 0x00000100UL
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#define TRC_RECORDER_COMPONENT_HEAP 0x00000200UL
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#define TRC_RECORDER_COMPONENT_INTERNAL_EVENT_BUFFER 0x00000400UL
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#define TRC_RECORDER_COMPONENT_INTERVAL 0x00000800UL
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#define TRC_RECORDER_COMPONENT_ISR 0x00001000UL
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#define TRC_RECORDER_COMPONENT_MULTI_CORE_EVENT_BUFFER 0x00002000UL
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#define TRC_RECORDER_COMPONENT_OBJECT 0x00004000UL
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#define TRC_RECORDER_COMPONENT_PRINT 0x00008000UL
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#define TRC_RECORDER_COMPONENT_STACK_MONITOR 0x00010000UL
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#define TRC_RECORDER_COMPONENT_STATE_MACHINE 0x00020000UL
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#define TRC_RECORDER_COMPONENT_STATIC_BUFFER 0x00040000UL
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#define TRC_RECORDER_COMPONENT_STRING 0x00080000UL
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#define TRC_RECORDER_COMPONENT_TASK 0x00100000UL
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#define TRC_RECORDER_COMPONENT_TIMESTAMP 0x00200000UL
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#define TRC_RECORDER_COMPONENT_COUNTER 0x00400000UL
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#define TRC_RECORDER_COMPONENT_TASK_MONITOR 0x00800000UL
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#define TRC_INTERNAL_EVENT_BUFFER_OPTION_TRANSFER_MODE_ALL (0U)
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#define TRC_INTERNAL_EVENT_BUFFER_OPTION_TRANSFER_MODE_CHUNKED (1U)
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/******************************************************************************
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* Supported ports
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*
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* TRC_HARDWARE_PORT_HWIndependent
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* A hardware independent fallback option for event timestamping. Provides low
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* resolution timestamps based on the OS tick.
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* This may be used on the Win32 port, but may also be used on embedded hardware
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* platforms. All time durations will be truncated to the OS tick frequency,
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* typically 1 KHz. This means that a task or ISR that executes in less than
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* 1 ms get an execution time of zero.
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*
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* TRC_HARDWARE_PORT_APPLICATION_DEFINED
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* Allows for defining the port macros in other source code files.
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*
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* TRC_HARDWARE_PORT_Win32
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* "Accurate" timestamping based on the Windows performance counter for Win32
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* builds. Note that this gives the host machine time, not the kernel time.
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*
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* Hardware specific ports
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* To get accurate timestamping, a hardware timer is necessary. Below are the
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* available ports. Some of these are "unofficial", meaning that
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* they have not yet been verified by Percepio but have been contributed by
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* external developers. They should work, otherwise let us know by emailing
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* support@percepio.com. Some work on any OS platform, while other are specific
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* to a certain operating system.
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*****************************************************************************/
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/****** Port Name ************************************* Code ** Official ** OS Platform *********/
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#define TRC_HARDWARE_PORT_APPLICATION_DEFINED 98
/* - - */
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#define TRC_HARDWARE_PORT_NOT_SET 99
/* - - */
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#define TRC_HARDWARE_PORT_HWIndependent 0
/* DEPRECATED */
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#define TRC_HARDWARE_PORT_Win32 1
/* Yes FreeRTOS on Win32 */
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#define TRC_HARDWARE_PORT_Atmel_AT91SAM7 2
/* No Any */
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#define TRC_HARDWARE_PORT_Atmel_UC3A0 3
/* No Any */
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#define TRC_HARDWARE_PORT_ARM_Cortex_M 4
/* Yes Any */
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#define TRC_HARDWARE_PORT_Renesas_RX600 6
/* Yes Any */
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#define TRC_HARDWARE_PORT_MICROCHIP_PIC32 7
/* Yes Any */
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#define TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_TMS570_RM48 8
/* Yes Any */
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#define TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_MSP430 9
/* No Any */
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#define TRC_HARDWARE_PORT_XILINX_PPC405 11
/* No FreeRTOS */
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#define TRC_HARDWARE_PORT_XILINX_PPC440 12
/* No FreeRTOS */
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#define TRC_HARDWARE_PORT_XILINX_MICROBLAZE 13
/* No Any */
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#define TRC_HARDWARE_PORT_XILINX_ZyncUltraScaleR5 14
/* No FreeRTOS */
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#define TRC_HARDWARE_PORT_NXP_LPC210X 15
/* No Any */
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#define TRC_HARDWARE_PORT_ARM_CORTEX_A9 16
/* Yes Any */
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#define TRC_HARDWARE_PORT_POWERPC_Z4 17
/* No FreeRTOS */
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#define TRC_HARDWARE_PORT_Altera_NiosII 18
/* Yes Any (Tested with FreeRTOS) */
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#define TRC_HARDWARE_PORT_ZEPHYR 19
/* Yes Zephyr */
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#define TRC_HARDWARE_PORT_XTensa_LX6 20
/* Yes ESP-IDF FreeRTOS */
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#define TRC_HARDWARE_PORT_XTensa_LX7 21
/* Yes ESP-IDF FreeRTOS */
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#define TRC_HARDWARE_PORT_Win64 22
/* Yes FreeRTOS on Win64 */
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#define TRC_HARDWARE_PORT_XMOS_XCOREAI 23
/* Yes FreeRTOS SMP */
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#define TRC_HARDWARE_PORT_RISCV_RV32I 24
/* Yes FreeRTOS */
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#define TRC_HARDWARE_PORT_CYCLONE_V_HPS 25
/* Yes FreeRTOS */
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#define TRC_HARDWARE_PORT_ARM_Cortex_M_NRF_SD 26
/* Yes FreeRTOS */
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#define TRC_HARDWARE_PORT_ARMv8AR_A32 27
/* Yes Any */
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#define TRC_HARDWARE_PORT_ADSP_SC5XX_SHARC 28
/* No FreeRTOS */
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#endif
/* TRC_PORTDEFINES_H */
include
trcDefines.h
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