Percepio Trace Recorder v4.11.0
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SEGGER_RTT.h
1/*********************************************************************
2* SEGGER Microcontroller GmbH *
3* The Embedded Experts *
4**********************************************************************
5* *
6* (c) 1995 - 2021 SEGGER Microcontroller GmbH *
7* *
8* www.segger.com Support: support@segger.com *
9* *
10**********************************************************************
11* *
12* SEGGER RTT * Real Time Transfer for embedded targets *
13* *
14**********************************************************************
15* *
16* All rights reserved. *
17* *
18* SEGGER strongly recommends to not make any changes *
19* to or modify the source code of this software in order to stay *
20* compatible with the RTT protocol and J-Link. *
21* *
22* Redistribution and use in source and binary forms, with or *
23* without modification, are permitted provided that the following *
24* condition is met: *
25* *
26* o Redistributions of source code must retain the above copyright *
27* notice, this condition and the following disclaimer. *
28* *
29* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
30* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
31* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
32* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
33* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
34* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
35* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
36* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
37* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
38* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
39* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
40* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
41* DAMAGE. *
42* *
43**********************************************************************
44* *
45* RTT version: 7.96o *
46* *
47**********************************************************************
48
49---------------------------END-OF-HEADER------------------------------
50File : SEGGER_RTT.h
51Purpose : Implementation of SEGGER real-time transfer which allows
52 real-time communication on targets which support debugger
53 memory accesses while the CPU is running.
54Revision: $Rev: 25842 $
55----------------------------------------------------------------------
56*/
57
58#ifndef SEGGER_RTT_H
59#define SEGGER_RTT_H
60
61#include "SEGGER_RTT_Conf.h"
62
63/*********************************************************************
64*
65* Defines, defaults
66*
67**********************************************************************
68*/
69
70#ifndef RTT_USE_ASM
71 //
72 // Some cores support out-of-order memory accesses (reordering of memory accesses in the core)
73 // For such cores, we need to define a memory barrier to guarantee the order of certain accesses to the RTT ring buffers.
74 // Needed for:
75 // Cortex-M7 (ARMv7-M)
76 // Cortex-M23 (ARM-v8M)
77 // Cortex-M33 (ARM-v8M)
78 // Cortex-A/R (ARM-v7A/R)
79 //
80 // We do not explicitly check for "Embedded Studio" as the compiler in use determines what we support.
81 // You can use an external toolchain like IAR inside ES. So there is no point in checking for "Embedded Studio"
82 //
83 #if (defined __CROSSWORKS_ARM) // Rowley Crossworks
84 #define _CC_HAS_RTT_ASM_SUPPORT 1
85 #if (defined __ARM_ARCH_7M__) // Cortex-M3
86 #define _CORE_HAS_RTT_ASM_SUPPORT 1
87 #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7
88 #define _CORE_HAS_RTT_ASM_SUPPORT 1
89 #define _CORE_NEEDS_DMB 1
90 #define RTT__DMB() __asm volatile ("dmb\n" : : :);
91 #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23
92 #define _CORE_HAS_RTT_ASM_SUPPORT 0
93 #define _CORE_NEEDS_DMB 1
94 #define RTT__DMB() __asm volatile ("dmb\n" : : :);
95 #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33
96 #define _CORE_HAS_RTT_ASM_SUPPORT 1
97 #define _CORE_NEEDS_DMB 1
98 #define RTT__DMB() __asm volatile ("dmb\n" : : :);
99 #elif (defined(__ARM_ARCH_8_1M_MAIN__)) // Cortex-M85
100 #define _CORE_HAS_RTT_ASM_SUPPORT 1
101 #define _CORE_NEEDS_DMB 1
102 #define RTT__DMB() __asm volatile ("dmb\n" : : :);
103 #else
104 #define _CORE_HAS_RTT_ASM_SUPPORT 0
105 #endif
106 #elif (defined __ARMCC_VERSION)
107 //
108 // ARM compiler
109 // ARM compiler V6.0 and later is clang based.
110 // Our ASM part is compatible to clang.
111 //
112 #if (__ARMCC_VERSION >= 6000000)
113 #define _CC_HAS_RTT_ASM_SUPPORT 1
114 #else
115 #define _CC_HAS_RTT_ASM_SUPPORT 0
116 #endif
117 #if (defined __ARM_ARCH_6M__) // Cortex-M0 / M1
118 #define _CORE_HAS_RTT_ASM_SUPPORT 0 // No ASM support for this architecture
119 #elif (defined __ARM_ARCH_7M__) // Cortex-M3
120 #define _CORE_HAS_RTT_ASM_SUPPORT 1
121 #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7
122 #define _CORE_HAS_RTT_ASM_SUPPORT 1
123 #define _CORE_NEEDS_DMB 1
124 #define RTT__DMB() __asm volatile ("dmb\n" : : :);
125 #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23
126 #define _CORE_HAS_RTT_ASM_SUPPORT 0
127 #define _CORE_NEEDS_DMB 1
128 #define RTT__DMB() __asm volatile ("dmb\n" : : :);
129 #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33
130 #define _CORE_HAS_RTT_ASM_SUPPORT 1
131 #define _CORE_NEEDS_DMB 1
132 #define RTT__DMB() __asm volatile ("dmb\n" : : :);
133 #elif (defined __ARM_ARCH_8_1M_MAIN__) // Cortex-M85
134 #define _CORE_HAS_RTT_ASM_SUPPORT 1
135 #define _CORE_NEEDS_DMB 1
136 #define RTT__DMB() __asm volatile ("dmb\n" : : :);
137 #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__)) // Cortex-A/R 32-bit ARMv7-A/R
138 #define _CORE_NEEDS_DMB 1
139 #define RTT__DMB() __asm volatile ("dmb\n" : : :);
140 #else
141 #define _CORE_HAS_RTT_ASM_SUPPORT 0
142 #endif
143 #elif ((defined __GNUC__) || (defined __clang__))
144 //
145 // GCC / Clang
146 //
147 #define _CC_HAS_RTT_ASM_SUPPORT 1
148 // ARM 7/9: __ARM_ARCH_5__ / __ARM_ARCH_5E__ / __ARM_ARCH_5T__ / __ARM_ARCH_5T__ / __ARM_ARCH_5TE__
149 #if (defined __ARM_ARCH_7M__) // Cortex-M3
150 #define _CORE_HAS_RTT_ASM_SUPPORT 1
151 #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7
152 #define _CORE_HAS_RTT_ASM_SUPPORT 1
153 #define _CORE_NEEDS_DMB 1 // Only Cortex-M7 needs a DMB but we cannot distinguish M4 and M7 here...
154 #define RTT__DMB() __asm volatile ("dmb\n" : : :);
155 #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23
156 #define _CORE_HAS_RTT_ASM_SUPPORT 0
157 #define _CORE_NEEDS_DMB 1
158 #define RTT__DMB() __asm volatile ("dmb\n" : : :);
159 #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33
160 #define _CORE_HAS_RTT_ASM_SUPPORT 1
161 #define _CORE_NEEDS_DMB 1
162 #define RTT__DMB() __asm volatile ("dmb\n" : : :);
163 #elif (defined __ARM_ARCH_8_1M_MAIN__) // Cortex-M85
164 #define _CORE_HAS_RTT_ASM_SUPPORT 1
165 #define _CORE_NEEDS_DMB 1
166 #define RTT__DMB() __asm volatile ("dmb\n" : : :);
167 #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__)) // Cortex-A/R 32-bit ARMv7-A/R
168 #define _CORE_NEEDS_DMB 1
169 #define RTT__DMB() __asm volatile ("dmb\n" : : :);
170 #else
171 #define _CORE_HAS_RTT_ASM_SUPPORT 0
172 #endif
173 #elif ((defined __IASMARM__) || (defined __ICCARM__))
174 //
175 // IAR assembler/compiler
176 //
177 #define _CC_HAS_RTT_ASM_SUPPORT 1
178 #if (__VER__ < 6300000)
179 #define VOLATILE
180 #else
181 #define VOLATILE volatile
182 #endif
183 #if (defined __ARM7M__) // Needed for old versions that do not know the define yet
184 #if (__CORE__ == __ARM7M__) // Cortex-M3
185 #define _CORE_HAS_RTT_ASM_SUPPORT 1
186 #endif
187 #endif
188 #if (defined __ARM7EM__)
189 #if (__CORE__ == __ARM7EM__) // Cortex-M4/M7
190 #define _CORE_HAS_RTT_ASM_SUPPORT 1
191 #define _CORE_NEEDS_DMB 1
192 #define RTT__DMB() asm VOLATILE ("DMB");
193 #endif
194 #endif
195 #if (defined __ARM8M_BASELINE__)
196 #if (__CORE__ == __ARM8M_BASELINE__) // Cortex-M23
197 #define _CORE_HAS_RTT_ASM_SUPPORT 0
198 #define _CORE_NEEDS_DMB 1
199 #define RTT__DMB() asm VOLATILE ("DMB");
200 #endif
201 #endif
202 #if (defined __ARM8M_MAINLINE__)
203 #if (__CORE__ == __ARM8M_MAINLINE__) // Cortex-M33
204 #define _CORE_HAS_RTT_ASM_SUPPORT 1
205 #define _CORE_NEEDS_DMB 1
206 #define RTT__DMB() asm VOLATILE ("DMB");
207 #endif
208 #endif
209 #if (defined __ARM8EM_MAINLINE__)
210 #if (__CORE__ == __ARM8EM_MAINLINE__) // Cortex-???
211 #define _CORE_HAS_RTT_ASM_SUPPORT 1
212 #define _CORE_NEEDS_DMB 1
213 #define RTT__DMB() asm VOLATILE ("DMB");
214 #endif
215 #endif
216 #if (defined __ARM7A__)
217 #if (__CORE__ == __ARM7A__) // Cortex-A 32-bit ARMv7-A
218 #define _CORE_NEEDS_DMB 1
219 #define RTT__DMB() asm VOLATILE ("DMB");
220 #endif
221 #endif
222 #if (defined __ARM7R__)
223 #if (__CORE__ == __ARM7R__) // Cortex-R 32-bit ARMv7-R
224 #define _CORE_NEEDS_DMB 1
225 #define RTT__DMB() asm VOLATILE ("DMB");
226 #endif
227 #endif
228// TBD: __ARM8A__ => Cortex-A 64-bit ARMv8-A
229// TBD: __ARM8R__ => Cortex-R 64-bit ARMv8-R
230 #else
231 //
232 // Other compilers
233 //
234 #define _CC_HAS_RTT_ASM_SUPPORT 0
235 #define _CORE_HAS_RTT_ASM_SUPPORT 0
236 #endif
237 //
238 // If IDE and core support the ASM version, enable ASM version by default
239 //
240 #ifndef _CORE_HAS_RTT_ASM_SUPPORT
241 #define _CORE_HAS_RTT_ASM_SUPPORT 0 // Default for unknown cores
242 #endif
243 #if (_CC_HAS_RTT_ASM_SUPPORT && _CORE_HAS_RTT_ASM_SUPPORT)
244 #define RTT_USE_ASM (1)
245 #else
246 #define RTT_USE_ASM (0)
247 #endif
248#endif
249
250#ifndef _CORE_NEEDS_DMB
251 #define _CORE_NEEDS_DMB 0
252#endif
253
254#ifndef RTT__DMB
255 #if _CORE_NEEDS_DMB
256 #error "Don't know how to place inline assembly for DMB"
257 #else
258 #define RTT__DMB()
259 #endif
260#endif
261
262#ifndef SEGGER_RTT_CPU_CACHE_LINE_SIZE
263 #define SEGGER_RTT_CPU_CACHE_LINE_SIZE (0) // On most target systems where RTT is used, we do not have a CPU cache, therefore 0 is a good default here
264#endif
265
266#ifndef SEGGER_RTT_UNCACHED_OFF
267 #if SEGGER_RTT_CPU_CACHE_LINE_SIZE
268 #error "SEGGER_RTT_UNCACHED_OFF must be defined when setting SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
269 #else
270 #define SEGGER_RTT_UNCACHED_OFF (0)
271 #endif
272#endif
273#if RTT_USE_ASM
274 #if SEGGER_RTT_CPU_CACHE_LINE_SIZE
275 #error "RTT_USE_ASM is not available if SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
276 #endif
277#endif
278
279#ifndef SEGGER_RTT_ASM // defined when SEGGER_RTT.h is included from assembly file
280#include <stdlib.h>
281#include <stdarg.h>
282#include <stdint.h>
283
284/*********************************************************************
285*
286* Defines, fixed
287*
288**********************************************************************
289*/
290
291//
292// Determine how much we must pad the control block to make it a multiple of a cache line in size
293// Assuming: U8 = 1B
294// U16 = 2B
295// U32 = 4B
296// U8/U16/U32* = 4B
297//
298#if SEGGER_RTT_CPU_CACHE_LINE_SIZE // Avoid division by zero in case we do not have any cache
299 #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (((NumBytes + SEGGER_RTT_CPU_CACHE_LINE_SIZE - 1) / SEGGER_RTT_CPU_CACHE_LINE_SIZE) * SEGGER_RTT_CPU_CACHE_LINE_SIZE)
300#else
301 #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (NumBytes)
302#endif
303#define SEGGER_RTT__CB_SIZE (16 + 4 + 4 + (SEGGER_RTT_MAX_NUM_UP_BUFFERS * 24) + (SEGGER_RTT_MAX_NUM_DOWN_BUFFERS * 24))
304#define SEGGER_RTT__CB_PADDING (SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(SEGGER_RTT__CB_SIZE) - SEGGER_RTT__CB_SIZE)
305
306/*********************************************************************
307*
308* Types
309*
310**********************************************************************
311*/
312
313//
314// Description for a circular buffer (also called "ring buffer")
315// which is used as up-buffer (T->H)
316//
317typedef struct {
318 const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4"
319 char* pBuffer; // Pointer to start of buffer
320 unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty.
321 unsigned WrOff; // Position of next item to be written by either target.
322 volatile unsigned RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host.
323 unsigned Flags; // Contains configuration flags. Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
324} SEGGER_RTT_BUFFER_UP;
325
326//
327// Description for a circular buffer (also called "ring buffer")
328// which is used as down-buffer (H->T)
329//
330typedef struct {
331 const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4"
332 char* pBuffer; // Pointer to start of buffer
333 unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty.
334 volatile unsigned WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host.
335 unsigned RdOff; // Position of next item to be read by target (down-buffer).
336 unsigned Flags; // Contains configuration flags. Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
337} SEGGER_RTT_BUFFER_DOWN;
338
339//
340// RTT control block which describes the number of buffers available
341// as well as the configuration for each buffer
342//
343//
344typedef struct {
345 char acID[16]; // Initialized to "SEGGER RTT"
346 int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2)
347 int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2)
348 SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via debug probe to host
349 SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from host via debug probe to target
350#if SEGGER_RTT__CB_PADDING
351 unsigned char aDummy[SEGGER_RTT__CB_PADDING];
352#endif
353} SEGGER_RTT_CB;
354
355/*********************************************************************
356*
357* Global data
358*
359**********************************************************************
360*/
361extern SEGGER_RTT_CB _SEGGER_RTT;
362
363/*********************************************************************
364*
365* RTT API functions
366*
367**********************************************************************
368*/
369#ifdef __cplusplus
370 extern "C" {
371#endif
372int SEGGER_RTT_AllocDownBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
373int SEGGER_RTT_AllocUpBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
374int SEGGER_RTT_ConfigUpBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
375int SEGGER_RTT_ConfigDownBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
376int SEGGER_RTT_GetKey (void);
377unsigned SEGGER_RTT_HasData (unsigned BufferIndex);
378int SEGGER_RTT_HasKey (void);
379unsigned SEGGER_RTT_HasDataUp (unsigned BufferIndex);
380void SEGGER_RTT_Init (void);
381unsigned SEGGER_RTT_Read (unsigned BufferIndex, void* pBuffer, unsigned BufferSize);
382unsigned SEGGER_RTT_ReadNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize);
383int SEGGER_RTT_SetNameDownBuffer (unsigned BufferIndex, const char* sName);
384int SEGGER_RTT_SetNameUpBuffer (unsigned BufferIndex, const char* sName);
385int SEGGER_RTT_SetFlagsDownBuffer (unsigned BufferIndex, unsigned Flags);
386int SEGGER_RTT_SetFlagsUpBuffer (unsigned BufferIndex, unsigned Flags);
387int SEGGER_RTT_WaitKey (void);
388unsigned SEGGER_RTT_Write (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
389unsigned SEGGER_RTT_WriteNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
390unsigned SEGGER_RTT_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
391unsigned SEGGER_RTT_ASM_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
392unsigned SEGGER_RTT_WriteString (unsigned BufferIndex, const char* s);
393void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
394unsigned SEGGER_RTT_PutChar (unsigned BufferIndex, char c);
395unsigned SEGGER_RTT_PutCharSkip (unsigned BufferIndex, char c);
396unsigned SEGGER_RTT_PutCharSkipNoLock (unsigned BufferIndex, char c);
397unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex);
398unsigned SEGGER_RTT_GetBytesInBuffer (unsigned BufferIndex);
399//
400// Function macro for performance optimization
401//
402#define SEGGER_RTT_HASDATA(n) (((SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff)
403
404#if RTT_USE_ASM
405 #define SEGGER_RTT_WriteSkipNoLock SEGGER_RTT_ASM_WriteSkipNoLock
406#endif
407
408/*********************************************************************
409*
410* RTT transfer functions to send RTT data via other channels.
411*
412**********************************************************************
413*/
414unsigned SEGGER_RTT_ReadUpBuffer (unsigned BufferIndex, void* pBuffer, unsigned BufferSize);
415unsigned SEGGER_RTT_ReadUpBufferNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize);
416unsigned SEGGER_RTT_WriteDownBuffer (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
417unsigned SEGGER_RTT_WriteDownBufferNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
418
419#define SEGGER_RTT_HASDATA_UP(n) (((SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff) // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
420
421/*********************************************************************
422*
423* RTT "Terminal" API functions
424*
425**********************************************************************
426*/
427int SEGGER_RTT_SetTerminal (unsigned char TerminalId);
428int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s);
429
430/*********************************************************************
431*
432* RTT printf functions (require SEGGER_RTT_printf.c)
433*
434**********************************************************************
435*/
436int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...);
437int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList);
438
439#ifdef __cplusplus
440 }
441#endif
442
443#endif // ifndef(SEGGER_RTT_ASM)
444
445//
446// For some environments, NULL may not be defined until certain headers are included
447//
448#ifndef NULL
449 #define NULL ((void*)0)
450#endif
451
452/*********************************************************************
453*
454* Defines
455*
456**********************************************************************
457*/
458
459//
460// Operating modes. Define behavior if buffer is full (not enough space for entire message)
461//
462#define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0) // Skip. Do not block, output nothing. (Default)
463#define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1) // Trim: Do not block, output as much as fits.
464#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2) // Block: Wait until there is space in the buffer.
465#define SEGGER_RTT_MODE_MASK (3)
466
467//
468// Control sequences, based on ANSI.
469// Can be used to control color, and clear the screen
470//
471#define RTT_CTRL_RESET "\x1B[0m" // Reset to default colors
472#define RTT_CTRL_CLEAR "\x1B[2J" // Clear screen, reposition cursor to top left
473
474#define RTT_CTRL_TEXT_BLACK "\x1B[2;30m"
475#define RTT_CTRL_TEXT_RED "\x1B[2;31m"
476#define RTT_CTRL_TEXT_GREEN "\x1B[2;32m"
477#define RTT_CTRL_TEXT_YELLOW "\x1B[2;33m"
478#define RTT_CTRL_TEXT_BLUE "\x1B[2;34m"
479#define RTT_CTRL_TEXT_MAGENTA "\x1B[2;35m"
480#define RTT_CTRL_TEXT_CYAN "\x1B[2;36m"
481#define RTT_CTRL_TEXT_WHITE "\x1B[2;37m"
482
483#define RTT_CTRL_TEXT_BRIGHT_BLACK "\x1B[1;30m"
484#define RTT_CTRL_TEXT_BRIGHT_RED "\x1B[1;31m"
485#define RTT_CTRL_TEXT_BRIGHT_GREEN "\x1B[1;32m"
486#define RTT_CTRL_TEXT_BRIGHT_YELLOW "\x1B[1;33m"
487#define RTT_CTRL_TEXT_BRIGHT_BLUE "\x1B[1;34m"
488#define RTT_CTRL_TEXT_BRIGHT_MAGENTA "\x1B[1;35m"
489#define RTT_CTRL_TEXT_BRIGHT_CYAN "\x1B[1;36m"
490#define RTT_CTRL_TEXT_BRIGHT_WHITE "\x1B[1;37m"
491
492#define RTT_CTRL_BG_BLACK "\x1B[24;40m"
493#define RTT_CTRL_BG_RED "\x1B[24;41m"
494#define RTT_CTRL_BG_GREEN "\x1B[24;42m"
495#define RTT_CTRL_BG_YELLOW "\x1B[24;43m"
496#define RTT_CTRL_BG_BLUE "\x1B[24;44m"
497#define RTT_CTRL_BG_MAGENTA "\x1B[24;45m"
498#define RTT_CTRL_BG_CYAN "\x1B[24;46m"
499#define RTT_CTRL_BG_WHITE "\x1B[24;47m"
500
501#define RTT_CTRL_BG_BRIGHT_BLACK "\x1B[4;40m"
502#define RTT_CTRL_BG_BRIGHT_RED "\x1B[4;41m"
503#define RTT_CTRL_BG_BRIGHT_GREEN "\x1B[4;42m"
504#define RTT_CTRL_BG_BRIGHT_YELLOW "\x1B[4;43m"
505#define RTT_CTRL_BG_BRIGHT_BLUE "\x1B[4;44m"
506#define RTT_CTRL_BG_BRIGHT_MAGENTA "\x1B[4;45m"
507#define RTT_CTRL_BG_BRIGHT_CYAN "\x1B[4;46m"
508#define RTT_CTRL_BG_BRIGHT_WHITE "\x1B[4;47m"
509
510
511#endif
512
513/*************************** End of file ****************************/